1. Field of the Invention
The present invention relates to a semiconductor device, especially to a method of fabricating a self-aligned silicide metal oxide semiconductor transistor (MOSFET) with an extended ultra-shallow S/D junction.
2. Description of the Prior Art
Metal oxide semiconductor field effect transistors (MOSFETs) have been traditionally used and widely applied in the semiconductor technologies. According to the trend of integrated circuits, the fabrication of the MOSFET also involves various issues such as short channel effect and the generation of parasitic capacitance. One of the issues is hot carriers that will inject into gate oxide, which is has been overcome by the development of light doped drain (LDD) structure.
The salicide with extension S/D junction structure has received a lot of attention, recently. With the advent of Ultra large Scale Integrated (ULSI) technologies, the sizes of semiconductor devices have gotten smaller and smaller than ever, resulting in the packing density of a wafer increasing continuously. Self aligned silicide (SALICIDE) technology is widely used to increase the packing density of ULSI circuits and to reduce the interconnect resistance for high speed operation. Please see the references by P. Fornara, et al., in IEDM Tech. Dig., p.73, 1996 and D. Hisamoto, et al., IEEE Trans. Electron Devices, vol. ED-44, p.951, 1997.
With the salicide structure, reduced parasitic and increased current drivability have made it possible to achieve extremely short gate delay times in a ring oscillator. However, salicide structures have not been perfected, mainly because the silicide layers used to reduce the resistance of the source/drain and gate electrode suffer from size effects. Furthermore, and as mentioned in the reference by G. E. Georgious, et al. J. Electrochem Soc., vol. 141, p.1351, 1994, the SALICIDE process will result in a higher junction leakage due to the metal penetration into the Si substrate to spike the junction and/or the residual metal or silicide across the LDD spacer causing the bridge between the adjacent devices.
The process to form the extended ultra-shallow source/drain junctions was suggested in the reference by A. Hori, et al., in IEDM Tech. Dig., p485, 1994. In this process, ultra shallow source/drain junctions were developed on the basis of 5 KeV ion implantation technology and rapid thermal annealing.